As known, the semiconductor electronic devices of EPROM and Flash EPROM memories comprise a plurality of non-volatile memory cells organized in matrices, i.e., the cells are organized in rows termed `word lines` and columns termed `bit lines.`
Each individual non-volatile memory cell comprises a MOS transistor in which a gate, which is located over a channel region, is floating, i.e., it presents a high impedance towards all other terminals of the same cell and of the circuit in which the cell is inserted.
The cell comprises also a second electrode, termed control gate, which is driven by appropriate control voltages. The other electrodes of the transistor are the usual drain, source and body terminals.
By applying appropriate voltages to the cell terminals it is possible to change a quantity of charge present in the floating gate, e.g., by utilizing the known Fowler-Nordheim Tunneling and/or Channel Hot Electrons Injection phenomena. This allows putting the transistor in two logical states: a first state with `high` threshold voltage and a second state with `low` threshold voltage.
Since the floating gate displays high impedance towards any other terminal of the cell, the charge stored therein can remain for an indefinite time even if the power supply of the circuit in which it is inserted is removed. The memory cell thus displays non-volatile memory characteristics.
The operation by means of which the charge is stored in the floating gate is termed `programming` while the operation by means of which the charge is removed from the floating gate is termed `erasing`.
Memory cells can be erased by ultraviolet (UV) radiation in EPROM memories or by electrical erasing in EEPROM or Flash-EPROM memories.
In recent years much effort has been expended to provide memory devices having an ever greater circuit density. This effort has led to the manufacturing of electrically programmable non-volatile memory matrices of the contactless type and with a so-called `cross-point` structure. An example of this kind of matrix and the associated manufacturing process is described in European Patent No. 0 573 728 filed by the assignee of the present application.
In this type of matrix the memory cells have source/drain regions provided in the substrate and contacted with unbroken, parallel diffusion strips, denominated bit lines, which coincide substantially with the matrix columns.
In memory matrices having a structure of the conventional type this function is provided by metallization strips which connect individual contacts formed in the drain regions of the cells belonging to the same column.
A contactless matrix calls for the presence of a virtual ground circuitry for the reading and programming steps. However, savings in circuitry surface area obtained from such a structure is considerable and results in a reduction of approximately one order of magnitude in the number of contacts to be created.
Another reference for this kind of circuit architecture is the article, "Alternate Metal Virtual Ground (AMG)"--A New Scaling Concept for Very High Density EPROM's," by Boaz Eitan, IEEE August 1991, Vol 12, No. 8, which is incorporated herein by reference.
In this kind of virtual ground matrix are defined parallel strips of a multilayer comprising tunnel oxide, a first polysilicon layer, an interpoly dielectric and a final layer of polysilicon termed Poly Cap. In openings between the various polysilicon strips is performed an implant, e.g., of arsenic if the substrate is the P-type, to provide diffusion of the bit lines.
The bit lines are contacted alternately and with a predetermined periodicity and indeed the contacts are present only at opposite ends of the bit lines and are provided in opposing contact regions which delimit the circuit area designed to house the memory cells.
Formation of the contacts at the ends of the bit lines imposes definition of extremely accurate contact openings which entail technological problems of alignment of the contacts and definition of the associated metallization lines.
To better understand the aspects of the present invention it is well to consider the fact that to obtain a contact with good current leakage characteristics on an N+ doping region subjected to reverse biasing, it is indispensable that the contact be entirely contained in this N+ region.
In other words, assuming that the N+ doped region is a region implanted on a P-substrate and is subjected to a positive (&gt;0) bias with respect to the ground biased substrate, if the contact were not contained with a good margin in the N+ region it could contact the P-substrate to give rise to a leakage current.
Accordingly, a good contact should always be contained within the N+ region while also allowing for design and manufacturing process tolerances. In a word, the contact can be provided with preset dimensional tolerances which should be considered in relation to the possible dimensional tolerances of the N+ region to be contacted and in relation to possible misalignments between the contact and the N+ region.
The prior art offers some solutions for avoiding shortcomings in the manufacturing of contacts in the virtual ground matrices.
A first solution calls for provision of an N+ area having a `head` portion with dimensions sufficiently greater than the surface area occupied by the contact.
An example of this type of solution is shown in the annexed FIGS. 1 and 1A.
FIG. 1 shows a plan view in enlarged scale of a detail of the layout of a portion 10 of an electronic memory circuit integrated on a semiconductor substrate 11. This portion 10 comprises contact regions at one end of the bit lines.
In the substrate 11 are provided active area strips 19 which could be replaced by pads provided only opposite the contact regions. Orthogonal to these strips 19 there are unbroken parallel diffusions of bit lines 12 provided by implantation and visible in FIG. 1A.
In the course of the manufacturing process there is provided on the substrate 11 a multilayer structure comprising in superimposed order gate oxide, polysilicon, interpoly dielectric and a final layer of Poly Cap. The bit lines 12 are provided through parallel openings provided in this multilayer structure.
It is important to note that FIG. 1A, although it is a cross section along plane of cut A-A' of FIG. 1, does not correspond thereto from a temporal viewpoint but refers to the final steps of the manufacturing and contact creation process in the course of which the multilayer structure has already been removed from the contact region.
In the contact region and above the silicon substrate uncovered, there is deposited a protective dielectric layer 13 which is subjected to a photolithographic process step followed by a chemical or plasma etching to define contact openings 14 adjacent to the bit lines 12.
A contact 15 is provided within each of the openings 14 to allow establishment of an electrical connection between a bit line 12 and a corresponding metallization strip 16 deposited over the dielectric layer 13.
FIG. 1 shows parallel strips 17 of a first layer of polysilicon or Poly1 extending parallel to the bit lines and overlying the active area strips 19 in a direction orthogonal thereto. Adjacent to each contact 15 the strips 17 display a narrowing which confers a certain spacing to contact regions 18 in the center of which is provided a contact 15.
This spacing entails essentially definition of a contact region 18 sufficiently wide to allow provision by implantation of a type N+ region 12 having dimensions sufficiently greater than those of the contact 15.
A second solution proposed by the prior art requires that the contacts be realized by implantation contacting the N+ doped bit line through an appropriate opening. This solution is shown schematically in FIGS. 2 to 4A and is particularly recommended when the lateral dimensions of the N+ region 12 do not ensure sufficient processing margin.
Specifically there are some planarization technologies for the dielectrics which fill interspaces between the polysilicon strips which do not allow provision of polysilicon interspaces of variable dimensions but require that the width of the interspace remain constant to optimize the filling process. In these cases the spacing between two Poly1 strips is the minimum allowed by the technology and is just enough to define the area occupied by the contact 15.
FIG. 2 shows clearly that the spacing between the polysilicon strips is constant and essentially as wide as the contact 15. Consequently the contact 15 must be provided by means of a self-aligned implantation step.
In an ideal situation this implantation allows providing a contact perfectly self-aligned with the corresponding active area as shown in FIG. 2A.
But in some cases, differently from the ideal case, there may be misalignment between the contact 15 and the corresponding active area 12. This situation is diagrammed in FIGS. 3 and 3A in which it can be seen that the contact 15 contacts both the region 12 and the substrate 11.
To avoid this shortcoming it is necessary to prepare an additional masking for the implantation only of the contacts of the N+ region as shown in FIGS. 4 and 4A.